A liquid Crystal Display (LCD) or an Organic Light-Emitting Diode (OLED) has the advantages of low radiation, a small volume, low energy consumption, etc., and has gradually superseded a traditional Cathode Ray Tube (CRT) display in some applications. LCD or OLED devices have been widely applied to notebook computers, Personal Digital Assistances (PDAs), flat televisions, mobile phones, and other information products. A practice of a traditional liquid crystal display is to drive a chip on a panel by an external drive chip to display an image, but in order to reduce the number of elements and lower the cost of manufacturing, the structure of the driver has gradually evolved in recent years to be fabricated directly on the display panel, for example, using the technology of Gate On Array in which a gate driver is integrated on a liquid crystal panel.
Ten (10) signal lines are required to drive a currently common gate drive apparatus into which a plurality of shift register units are connected. FIG. 1 illustrates a gate drive apparatus including an even number N of shift register units, where N is indivisible by 4. In the gate drive apparatus, a forward select signal terminal GN−1 of each of the shift register units other than the first two shift register units receives the signal output by the second shift register unit preceding to the shift register unit; and a backward select signal terminal GN+1 of each of the shift register units other than the last two shift register units receives the signal output by the second shift register unit succeeding to the shift register unit. A forward select signal terminal GN−1 of the first shift register unit in the gate drive apparatus receives a first initial trigger signal STV1, and a forward select signal terminal GN−1 of the second shift register unit in the gate drive apparatus receives a second initial trigger signal STV2; and if there are an even number of shift register units included in the gate drive apparatus, then a backward select signal terminal GN+1 of the last shift register unit in the gate drive apparatus receives the second initial trigger signal STV2, and a backward select signal terminal GN+1 of the second last shift register unit in the gate drive apparatus receives the first initial trigger signal STV1; or if there are an odd number of shift register units included in the gate drive apparatus, then the backward select signal terminal GN+1 of the last shift register unit in the gate drive apparatus receives the first initial trigger signal STV1, and the backward select signal terminal GN+1 of the second last shift register unit in the gate drive apparatus receives the second initial trigger signal STV2. A forward scan signal FW terminal of each of the shift register units in the gate drive apparatus receives a forward scan signal FW, and a backward scan signal BW terminal of each of the shift register units receives a backward scan signal BW; and when the forward scan signal FW is at a high level, the backward scan signal BW is at a low level, and the gate drive apparatus scans forward a scan line, and when the forward scan signal FW is at the low level, the backward scan signal BW is at the high level, and the gate drive apparatus scans backward the scan line. A reset signal RST terminal of each of the shift register units in the gate drive apparatus receives a reset signal RST, and a low level signal VGL terminal of each of the shift register units receives a low level signal.
In the gate drive apparatus illustrated in FIG. 1, a clock block signal CLKB of each of the shift register units receives a mod((N−1)/4)-th clock signal, and a clock signal CLK of each of the shift register units receives a mod((mod((N−1)/4)+2)/4)-th clock signal, for example, for the first shift register unit, N=1, and then the clock block signal CLKB of the shift register unit receives a zero-th clock signal CLK0, and the clock signal CLK of the shift register unit receives a second clock signal CLK2; for the second shift register unit, N=2, and then the clock block signal CLKB of the shift register unit receives a first clock signal CLK1, and the clock signal CLK of the shift register unit receives a third clock signal CLK3; for the third shift register unit, N=3, and then the clock block signal CLKB of the shift register unit receives the second clock signal CLK2, and the clock signal CLK of the shift register unit receives the zero-th clock signal CLK0; and for the fourth shift register unit, N=4, and then the clock block signal CLKB of the shift register unit receives the third clock signal CLK3, and the clock signal CLK of the shift register unit receives the first clock signal CLK1, where when the zero-th clock signal is at the high level, the second clock signal is at the low level, and when the second clock signal is at the high level, the zero-th clock signal is at the low level; and when the first clock signal is at the high level, the third clock signal is at the low level, and when the third clock signal is at the high level, the first clock signal is at the low level; and the reset signal RST can control the respective shift register units in the gate drive apparatus to be reset to output low level signals.
In summary, since the 10 signal lines including the forward scan signal FW, the backward scan signal BW, the first initial trigger signal STV1, the second initial trigger signal STV2, the zero-th clock signal CLK0, the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the low level signal VGL and the reset signal RST are required to drive the currently common gate drive apparatus, they occupy a width of approximately 0.3 mm in a display panel, and this may result in wider edge frames of the display panel using the gate drive apparatus and consequently in a larger amount of consumed raw materials in manufacturing a display apparatus including the gate drive apparatus, thus making the display apparatus relatively costly.